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24AA256/24LC256/24FC256
8.0
READ OPERATION
8.2
Random Read
Read operations are initiated in much the same way as
write operations, with the exception that the R/W bit of
the control byte is set to ‘ 1 ’. There are three basic types
of read operations: current address read, random read
and sequential read.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX256 as part of a write operation (R/W bit set to
‘ 0 ’). Once the word address is sent, the master gener-
8.1
Current Address Read
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the
The 24XX256 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘ 1 ’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1 .
Upon receipt of the control byte with R/W bit set to ‘ 1 ’,
the 24XX256 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a one.
The 24XX256 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, though it does generate a
Stop condition, which causes the 24XX256 to discon-
tinue transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
24XX256 discontinues transmission (Figure 8-1).
8.3
Sequential Read
FIGURE 8-1:
S
CURRENT ADDRESS
READ
Sequential reads are initiated in the same way as a
random read except that after the 24XX256 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
Bus Activity
Master
T
A
R
Control
Byte
Data
Byte
S
T
O
read. This acknowledge directs the 24XX256 to
transmit the next sequentially addressed 8-bit word
S 1 0 1 0 A AA 1
SDA Line
Bus Activity
T
2 1 0
A
C
K
N
O
A
C
K
P
P
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX256 contains an internal Address
Pointer which is incremented by one at the completion
of each operation. This Address Pointer allows the
entire memory contents to be serially read during one
operation. The internal Address Pointer will
automatically roll over from address 7FFF to address
0000 if the master acknowledges the byte received
from the array address 7FFF.
FIGURE 8-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
Control
Byte
Address
High Byte
Address
Low Byte
S
T
A
R
Control
Byte
Data
Byte
S
T
O
T
T
P
SDA Line
S 1 01 0 AAA 0
2 1 0
x
S 1 0 1 0 A A A 1
2 1 0
P
A
A
A
A
N
Bus Activity
x = “don’t care” bit
C
K
C
K
C
K
C
K
O
A
C
K
FIGURE 8-3:
SEQUENTIAL READ
Bus Activity
Master
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
Data (n + x )
S
T
O
P
SDA Line
P
A
C
A
C
A
C
A
C
N
O
Bus Activity
K
K
K
K
A
C
K
DS21203R-page 12
? 1998-2011 Microchip Technology Inc.
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